matchList.add(new VerilogCompletionProposal(parameter, offset, replace.length()));
}
}
}else if (element instanceof VerilogTaskElement) {
VerilogTaskElement task = (VerilogTaskElement) element;
for(OutlineElement child: task.getChildren()){
//add signals
if (child instanceof VerilogSignalElement && child.getName().startsWith(replace)) {
VerilogSignalElement signal = (VerilogSignalElement) child;
matchList.add(new VerilogCompletionProposal(signal, offset, replace.length()));
}