VerilogPortElement port = (VerilogPortElement) child;
matchList.add(new VerilogCompletionProposal(port, offset, replace.length()));
}else if (child instanceof VerilogSignalElement && child.getName().startsWith(replace)) {
//add signals
VerilogSignalElement signal = (VerilogSignalElement) child;
matchList.add(new VerilogCompletionProposal(signal, offset, replace.length()));
}else if (element instanceof VerilogParameterElement) {
//add parameter
VerilogParameterElement parameter = (VerilogParameterElement) element;
matchList.add(new VerilogCompletionProposal(parameter, offset, replace.length()));
}
}
}else if (element instanceof VerilogTaskElement) {
VerilogTaskElement task = (VerilogTaskElement) element;
for(OutlineElement child: task.getChildren()){
//add signals
if (child instanceof VerilogSignalElement && child.getName().startsWith(replace)) {
VerilogSignalElement signal = (VerilogSignalElement) child;
matchList.add(new VerilogCompletionProposal(signal, offset, replace.length()));
}
}
}else if (element instanceof VerilogFunctionElement) {
VerilogFunctionElement func = (VerilogFunctionElement) element;
for(OutlineElement child: func.getChildren()){
//add signals
if (child instanceof VerilogSignalElement && child.getName().startsWith(replace)) {
VerilogSignalElement signal = (VerilogSignalElement) child;
matchList.add(new VerilogCompletionProposal(signal, offset, replace.length()));
}
}
}