Examples of VerilogPortElement

      if (element instanceof VerilogModuleElement) {
        VerilogModuleElement module = (VerilogModuleElement) element;
        for(OutlineElement child: module.getChildren()){          
          if (child instanceof VerilogPortElement && child.getName().startsWith(replace)) {
            //add ports
            VerilogPortElement port = (VerilogPortElement) child;
            matchList.add(new VerilogCompletionProposal(port, offset, replace.length()));
            
          }else if (child instanceof VerilogSignalElement && child.getName().startsWith(replace)) {
            //add signals
            VerilogSignalElement signal = (VerilogSignalElement) child;

Examples of net.sourceforge.veditor.parser.verilog.VerilogOutlineElementFactory.VerilogPortElement

          // localparam is not included parameter list
          if (!p.isLocal())
            parameters.add(p);            
        }
        if (child instanceof VerilogPortElement) {
          VerilogPortElement p = (VerilogPortElement) child;
          ports.add(p);
        }
      }
              
      isParams = isParams && (parameters.size() > 0);

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