Examples of VerilogModuleElement

Examples of net.sourceforge.veditor.parser.verilog.VerilogOutlineElementFactory.VerilogModuleElement

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    while (element != null)
    {
      // FIX!!! should we do something more advanced when there
      // are no modules?
      if (element instanceof VerilogModuleElement) {
        VerilogModuleElement module = (VerilogModuleElement) element;
        for(OutlineElement child: module.getChildren()){         
          if (child instanceof VerilogPortElement && child.getName().startsWith(replace)) {
            //add ports
            VerilogPortElement port = (VerilogPortElement) child;
            matchList.add(new VerilogCompletionProposal(port, offset, replace.length()));
           
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Examples of net.sourceforge.veditor.parser.verilog.VerilogOutlineElementFactory.VerilogModuleElement

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  {
    //default behavior
    StringBuffer replace=new StringBuffer(m_Element.getName());
   
    if(m_Element instanceof VerilogModuleElement){
      VerilogModuleElement module = (VerilogModuleElement) m_Element;
      String name = module.getName();
      String indent = "\n" + getIndentString();
      boolean isParams = VerilogPlugin
          .getPreferenceBoolean("ContentAssist.ModuleParameter");
     
      ArrayList<VerilogParameterElement> parameters=new ArrayList<VerilogParameterElement>();
      ArrayList<VerilogPortElement> ports=new ArrayList<VerilogPortElement>();
      for(OutlineElement child : module.getChildren()){
        if (child instanceof VerilogParameterElement) {
          VerilogParameterElement p = (VerilogParameterElement) child;

          // localparam is not included parameter list
          if (!p.isLocal())
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Examples of net.sourceforge.veditor.parser.verilog.VerilogOutlineElementFactory.VerilogModuleElement

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  public boolean hasChildren(Object element)
  {
    //if we have a module, it must have instatiations
    if (element instanceof VerilogModuleElement) {
      VerilogModuleElement moduleElement = (VerilogModuleElement) element;
      for(OutlineElement child : moduleElement.getChildren()){
        if(child instanceof VerilogInstanceElement){
          return true;
        }
      }
    }
    //if we have an instance, find the module that goes with it
    if (element instanceof VerilogInstanceElement) {
      VerilogInstanceElement instance = (VerilogInstanceElement) element;
      //get the module
      if(m_ModuleList.containsKey(instance.getModuleType())){
        //if the module has instantiations
        VerilogModuleElement moduleElement=m_ModuleList.get(instance.getModuleType());
        for(OutlineElement child : moduleElement.getChildren()){
          if(child instanceof VerilogInstanceElement){
            VerilogInstanceElement childInstance = (VerilogInstanceElement) child;
            //guard against recursive definitions
            if(childInstance.getModuleType().equals(moduleElement.getName()) ==false){
              return true;
            }
          }
        }
      }
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Examples of net.sourceforge.veditor.parser.verilog.VerilogOutlineElementFactory.VerilogModuleElement

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  {
    ArrayList<VerilogOutlineElement> children=new ArrayList<VerilogOutlineElement>();
   
    //if we have a module, it must have instatiations
    if (parentElement instanceof VerilogModuleElement) {
      VerilogModuleElement moduleElement = (VerilogModuleElement) parentElement;
      for(OutlineElement child : moduleElement.getChildren()){
        if(child instanceof VerilogInstanceElement){
          VerilogInstanceElement instance = (VerilogInstanceElement) child;
          children.add(instance);
        }
      }
    }
    //if we have an instance, find the module that goes with it
    if (parentElement instanceof VerilogInstanceElement) {
      VerilogInstanceElement instance = (VerilogInstanceElement) parentElement;
      //get the module
      if(m_ModuleList.containsKey(instance.getModuleType())){
        //if the module has instantiations
        VerilogModuleElement moduleElement=m_ModuleList.get(instance.getModuleType());
        for(OutlineElement child : moduleElement.getChildren()){
          if(child instanceof VerilogInstanceElement){
            VerilogInstanceElement childInstance = (VerilogInstanceElement) child;
            children.add(childInstance);
          }
        }
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Examples of net.sourceforge.veditor.parser.verilog.VerilogOutlineElementFactory.VerilogModuleElement

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    //scan for modules and make a list
    topLevelElements = database.findTopLevelElements("");
    m_ModuleList.clear();
    for (OutlineElement element : topLevelElements){
      if (element instanceof VerilogModuleElement) {
        VerilogModuleElement moduleElement = (VerilogModuleElement) element;
        m_ModuleList.put(moduleElement.getShortName(),moduleElement);
      }
    }
    ////////////////////////////////////////////
    // scan the modules list and remove the ones that
    // are instatiated in another module
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