Examples of net.sourceforge.veditor.parser.verilog.VerilogOutlineElementFactory.VerilogParameterElement

            //add signals
            VerilogSignalElement signal = (VerilogSignalElement) child;
            matchList.add(new VerilogCompletionProposal(signal, offset, replace.length()));  
          }else if (element instanceof VerilogParameterElement) {
            //add parameter
            VerilogParameterElement parameter = (VerilogParameterElement) element;
            matchList.add(new VerilogCompletionProposal(parameter, offset, replace.length()));
          }          
        }
        
      }else if (element instanceof VerilogTaskElement) {

      
      ArrayList<VerilogParameterElement> parameters=new ArrayList<VerilogParameterElement>();
      ArrayList<VerilogPortElement> ports=new ArrayList<VerilogPortElement>();
      for(OutlineElement child : module.getChildren()){
        if (child instanceof VerilogParameterElement) {
          VerilogParameterElement p = (VerilogParameterElement) child;


          // localparam is not included parameter list
          if (!p.isLocal())
            parameters.add(p);            
        }
        if (child instanceof VerilogPortElement) {
          VerilogPortElement p = (VerilogPortElement) child;
          ports.add(p);

Related Classes of net.sourceforge.veditor.parser.verilog.VerilogOutlineElementFactory.VerilogParameterElement

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